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[VHDL-FPGA-Verilog] adder

Description: FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
Platform: | Size: 1024 | Author: surya | Hits:

[Software Engineering] FPGAFIR

Description: FPGA-based high-order FIR filter design
Platform: | Size: 4537344 | Author: 玉玲 | Hits:

[VHDL-FPGA-Verilog] verilog.DA.FIR..

Description: 用verilog写的16阶串行DA算法FIR滤波器-Verilog written by 16-order FIR filter serial DA algorithm
Platform: | Size: 576512 | Author: 代鑫 | Hits:

[Embeded-SCM Develop] fir

Description: 使用verilog语言实现的fir滤波器，使用了内部的触发器资源，优化。-Verilog language used to achieve the fir filter, the use of internal resources of the flip-flop, and optimize.
Platform: | Size: 1024 | Author: liang jianbing | Hits:

[VHDL-FPGA-Verilog] fir_hdl

Description: 一个 FIR 滤波器的 verilog 实现， 与 matlab 产生的 reference code 相互验证。-Verilog a FIR filter to achieve, with the reference code generated by matlab mutual authentication.
Platform: | Size: 97280 | Author: wei | Hits:

[VHDL-FPGA-Verilog] fir

Description: 16阶FIR VHDL程序并附带testbench，并有简单流水线设计！-16 Tap FIR vhdl code with testbench and pipelining design
Platform: | Size: 352256 | Author: hongwan | Hits:

[Books] fir

Description: 本文以软件无线电为指导，提出基于CORDIC算法利用FPGA平台数字下变频器设计方案。首先分析下变频器的结构；然后采用模块化设计思想，将数字下变 频的功能模块包括数字控制振荡器、CIC抽取滤波、HBF抽取滤波器、FIR低通滤波器进行分析和FPGA的设计；最后在 MATLAB/DSPBuilder下硬件仿真模块进行仿真并给出仿真结果。-In this paper, software-defined radio as the guidance, based on the CORDIC algorithm uses the FPGA platform, digital down-converter design. First analyzes the structure of down-converter and then use a modular design concept, the digital down-conversion function modules including digital controlled oscillator, CIC decimation filtering, HBF decimation filter, FIR low-pass filter for analysis and FPGA design the final In the MATLAB/DSPBuilder under the hardware emulation module simulation and simulation results.
Platform: | Size: 201728 | Author: jiang | Hits:

[Program doc] DSP--base--on-FPGA

Description: 这是一本国外的经典教材，讲述了现阶段所有数字信号处理的FPGA实现，从第二章讲述二进制的算法到现阶段数字信号处理的研究热点，基于FPGA实现！包括FIR，自适应滤波，纠错码，调制解调，加密，傅立叶变换等等。更难能可贵的是每个例子都有VHDL和Verilog代码-This is a classic foreign materials, described at this stage all the digital signal processing FPGA, from the second chapter about the binary digital signal processing algorithms to the current stage of research focus, based on FPGA implementation! Including FIR, adaptive filtering, error-correcting codes, modulation and demodulation, encryption, Fourier transform and so on. Even more valuable is that each case has a VHDL and Verilog code! !
Platform: | Size: 7067648 | Author: 刘伟 | Hits:

[VHDL-FPGA-Verilog] Xilinx-FIR

Description: 基于Xilinx FPGA实现的系数可装载数字滤波器源代码-Configurable Digital Filter Based on FPGA (using Verilog under Matlab 2008a)
Platform: | Size: 3090432 | Author: 胡文静 | Hits:

[Algorithm] fir_filter_verilog

Description: FIR filter verilog project
Platform: | Size: 34816 | Author: Yoshi | Hits:

[VHDL-FPGA-Verilog] cic_intp_64_four

Description: 4阶CIC内插滤波器，内插系数64，Verilog版本，数字下变频-4-order interpolating CIC filter interpolation factor of 64, Verilog version of the digital down-conversion
Platform: | Size: 1024 | Author: 王刚 | Hits:

[VHDL-FPGA-Verilog] fir_dec3

Description: FIR抽取滤波器，抽取系数3，Verilog版本，数字下变频-FIR decimation filter, extraction coefficient of 3, Verilog version of the digital down-conversion
Platform: | Size: 2048 | Author: 王刚 | Hits:

[VHDL-FPGA-Verilog] FIR64tap

Description: 使用verilog语言实现64阶FIR,调试可以通过-64 taps FIR with verilog
Platform: | Size: 19456 | Author: 黄锦江 | Hits:

[Communication] Verilog_Hdl48FIR

Description: verilog hdl fir 48阶-verilog hdl fir
Platform: | Size: 90112 | Author: 张兵 | Hits:

[assembly language] fir

Description: 做作业的时候用VERILOG编写的FIR滤波器程序，希望对大家有用-Homework time FIR filter with VERILOG written procedures, we want to be useful
Platform: | Size: 1024 | Author: 龙兰飞 | Hits:

[VHDL-FPGA-Verilog] FIR

Description: 实现FIR滤波，利用Verilog语言对其进行了设计 -FIR filter implementation using Verilog language design was carried out
Platform: | Size: 4126720 | Author: 翁萍 | Hits:

[VHDL-FPGA-Verilog] VerilogFIR

Description: low pass FIR filter programmed by Verilog, you can change the coefficients in the program to achieve different response
Platform: | Size: 4225024 | Author: 吴恒 | Hits:

[VHDL-FPGA-Verilog] dilbalu_fir7

Description: basic fir filtering in verilog fpga in vhdl
Platform: | Size: 142336 | Author: dileepkumar | Hits:

[Editor] FIR-verilog

Description: FIR filter verilog code
Platform: | Size: 711680 | Author: jeren1228 | Hits:

[VHDL-FPGA-Verilog] fir filter design

Description: FIR FILTER DESIGN IN VERILOG ON FPGA
Platform: | Size: 18432 | Author: GIRISH | Hits:
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